EE 370 Lab 2

SSI and MSI Implementation

Pre-lab: 12 pts

Do the Karnaugh maps (where appropriate) and provide completed circuit diagrams including pin numbers for each step. All of these items will be collected at the start of lab. Make a copy for your own use during lab. Be prepared to demonstrate operation of the various circuits and features.

In-lab:

  1. MUX Implementation. Implement the function from Lab #1 using a 74151 8-to-1 multiplexer using an appropriate Karnaugh map (Roth 9.4) to determine the input values you need to use. Connect variables A, B, and C to S0, S1, and S2, respectively. (Note that this 16-pin DIP has Vcc and GND on pins 16 and 8, respectively.) Show your Karnaugh map and your connections on the diagrams below before coming to lab. When the circuit is working, show it to the lab instructor.

    Karnaugh map:

  2. Repeat the previous step connecting variables B, C, and D to S0, S1, and S2, respectively.

    Karnaugh map:

  3. Decoder Implementation. Simultaneously implement the following three functions with a 74138 3-to-8 line decoder (see Roth 9.5) and a 7410 triple three-input NAND. Complete the circuit diagram below before coming to lab by adding lines and pin numbers. When the circuit is working, have the lab instructor check it. (Note again that Vcc and GND are pins 16 and 8, respectively, for this chip.)

    f = A'B'C + ABC + A'BC
    g = AB'C + A'B'C
    h = A'C + A'BC'


  4. SR flip-flop with enable. The SR flip-flop (Roth 11.2) responds to its S and R inputs continuously. An input can be added so that the S and R inputs are only used when this enabling (or clock) input is high. Construct such a flip-flop, as shown in the following circuit diagram. Use logic switches to provide the S-R inputs and a debounced pushbutton with a 4.7K-ohm pullup resistor for the clock. Use logic indicators to show the outputs Q and Q'. Verify the operation against the characteristic table.



  5. Discrete Master-slave JK flip-flop. Implement the following circuit (similar to the one found in Roth 11.6) using two copies of your circuit from the step above plus the appropriate additional gates. Use logic switches to provide the J-K inputs and a debounced pushbutton with 4.7K-ohm pullup resistor for the clock. Use logic indicators to show the outputs Master Q (P), Slave Q, and Slave Q'. Verify operation, including one's catching and toggling. (See Wakerly 7.2.7) Demonstrate your working circuit to the lab instructor.



  6. IC Master-slave JK flip-flop. Same exercise as above, but use a 7476 which contains two JK flip-flops. Only one needs to be connected and exercised. Verify operation against the JK flip-flop characteristic table. (Note that Vcc and GND are pins 5 and 13, respectively for this chip.)










  7. Checkpoint. Take a moment to look over the lab and review what you have learned. Call the lab instructor who will verify your knowledge and then initial the checkpoint.


Beginning of Lab
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